A standard DRAM utilizes a charge storage cell for storing a data bit, which cell is comprised of a cell access field effect transistor (FET) which has its gate connected to a word line and its drain connected to a bit line. A capacitor, created using field effect technology, is connected between the source of the FET and a cell plate voltage source or V.sub.cp.
In applications involving DRAMs embedded in ASICs, since the integrated circuit substrate is connected to ground, the memory cell array is implemented using p-channel capacitors and access devices. The array is therefore contained in an n-well which is biased to a positive voltage to prevent latchup. In such a PMOS array, the DRAM word line, which is held at V.sub.DD in the off state, must be brought to a negative voltage which is more negative than V.sub.SS in the active state in order to fully turn on the cell access FET, and to allow a full V.sub.SS voltage level to be stored by the cell.
However, the negative voltage cannot be generated in CMOS circuits employing both NMOS and PMOS devices since the p-substrate is connected to V.sub.SS. A negative voltage cannot be connected to any n-channel source or drain because it would forward bias to the substrate. P-channel dynamic circuits must therefore be used to generate the negative voltage used by the word line driver.
A structure for generating the negative voltage using all p-channel FETs is described in the specification of U.S. patent application entitled "Memory Cell And Wordline Driver For Embedded Dram in ASIC Process", Ser. No. 08/355,956 filed Dec. 14, 1994, invented by Karl Skjaveland et al. The structure from that application, over which the present invention is an improvement, is reproduced in FIGS. 1A and 1B herein, using reference numerals similar to those in the aforenoted patent application.
FIG. 1A illustrates a word line voltage generating circuit from the aforenoted patent application that uses only p-channel FETs.
The top plate (gate) of a p-channel FET capacitor 30 is connected to the X+ node which is an input to the circuit of FIG. 1B. A CMOS inverter 45 has its output connected to the bottom plate (source-drain) of capacitor 30. The source-drain circuit of p-channel FET 36 is connected between the input of capacitor 30 and the gate 34 of p-channel FET 34. The gate of FET 36 is connected to ground. The drain of FET 34 is connected to the node X+.
Also connected to the node X+ is the drain of p-channel PET 28, the source of which is connected to voltage source V.sub.DD.
The gate of FET 28, the input to inverter 45 and the source of FET 34 are each driven by respective inverters 47, 48 and 49.
The input to the circuit for receiving an Xi signal, a secondary row address signal generated at the beginning of an active cycle, is connected through a pair of serially connected inverters 50, the output of which is connected both to the input of inverter 49 and to the input of serially connected inverters 51, as well as to an input of NOR gate 53. The other input to NOR gate 53 is connected to the Xi node. The output of the pair of inverters 51 is connected to an input of NAND gate 55 which has its output connected to the input of inverter 48. The other input to gates 53 and 55 are connected to the input for receiving signal Xi.
FIG. 1B illustrates a word line driving circuit, and FIG. 1C is a timing chart from the aforenoted patent application. Voltage X+ is applied via the source-drain circuit of an FET 23 to the word line 3. The word line is selectively connected to VDD via the source-drain circuit of an FET 24. A wordline address signal Xj is decoded from word line address circuitry, and the predecoder generate signal PDXG are combined by a NAND gate 26 whose output is applied to the gate of FET 23 via the source-drain circuit of FET 25. A word line reset voltage PUB derived from the address signal is applied to the gate of FET 24 via inverter 40. Ground is applied to the gate of FET 25.
Prior to a cycle, the address signal related input to inverter 40 is high, causing conduction of FET 24. Node Xg is high causing FET 23 to be non-conductive. The word line 3 is thus held at about VDD voltage level during standby.
At the start of a row cycle, both the decoded address signal Xj and PDXG go high, the input to inverter 40 goes low, PUB node goes high, and FET 24 becomes non-conductive.
At approximately this time the word line signal X+ then becomes boosted to a voltage negatively greater than ground (V.sub.SS as will be described below. Now assuming that the ratio of gate oxide capacitance to stray capacitance plus FET 25 drain capacitance is high, node Xg will track the X+ voltage, due to capacitive coupling in FET 23, i.e. it will perform self-boosting. This will allow FET 23 to pass the boosted voltage X+ to the word line 3.
During standby, the secondary row decoder signal Xi in the voltage generator circuit (FIG. 1A) is low. This maintains node RB low and thus precharges X+ to VDD through FET 28. Nodes DR and CSD- are high and low respectively. At the beginning of the active cycle, Xi goes high. As a result, the following sequence of events occur: node RB goes high, thus turning off FET 28. DR goes high while CSD- is still low. This allows FET 34 to first set the X+ voltage to V.sub.SS.
Shortly thereafter, as a result of the propagation delay through inverters 51 and NAND gate 55 and inverter 48, CSD- goes high, switching off FET 36. Furthermore, CSD (the output of inverter 45) now goes from high to low, and since it is connected to one side of the boost capacitor 30, boosts the X+ line negatively. Once this has occurred, this negatively boosted voltage is passed on to the word line driver and on to the word line itself via FET 23 (FIG. 1B).
It should be noted however, that once the X+ line is boosted negatively at the beginning of the active cycle, it has no path to accept any positive charge; in other words, X+ will remain boosted negatively until the end of the active cycle. This extended negative voltage can damage the capacitor integrity of devices in ASIC processes which are not designed to withstand negative voltages for long periods of time.